RustV OS Lab is a RISC-V operating system prototype written in Rust. It follows the bare-metal learning path: take control at 0x8000_0000, clear .bss, enter Rust, talk through the QEMU virt UART, model physical pages, sketch Sv39 page tables, route traps, and build a small scheduler/syscall layer.
- RISC-V
virtmemory map notes and linker script - Assembly boot path that parks secondary harts and clears
.bss no_stdRust kernel entry point and panic handler- NS16550a UART console with
print!andprintln! - MMIO helpers using volatile reads/writes
- Page-grained physical allocator model
- Sv39 page-table entry helpers and virtual-address decoding
- Trap cause decoding and trap frame model
- Cooperative task scheduler model
- Minimal syscall dispatcher
- QEMU, GDB, and build workflow documentation
push_project.shconfigured for the requested repository and date window
rustup install nightly
rustup target add riscv64gc-unknown-none-elf
cargo install cargo-binutilsYou also need QEMU:
sudo apt install qemu-system-misccargo buildmake runsrc/
asm/boot.S Boot hart selection and BSS clearing
console/ UART-backed formatting macros
drivers/ MMIO and NS16550a UART driver
lds/virt.lds QEMU virt linker script
memory/ Page allocator, regions, Sv39 helpers
riscv/ CSR wrappers and wait-for-interrupt helpers
sync/ Spin lock primitive
syscall/ Educational syscall model
task/ Cooperative scheduler model
trap/ Trap frame and trap cause decoding- Boot one hart and park the rest.
- Clear
.bss, set the stack pointer, and jump into Rust. - Initialize UART output through MMIO.
- Decode traps and page faults.
- Manage physical pages with descriptors.
- Build Sv39 mappings for kernel text, data, heap, and MMIO.
- Add a timer tick and cooperative task scheduler.
- Add user-mode experiments and syscall validation.
- Explore virtio block and network devices.
This repository is a lab, not a production OS. The point is to make each kernel subsystem visible, readable, and easy to extend.